Index 
   4

4004.............................................................41


    6

6502    xiv, 24, 33, 41, 159, 160, 169, 176, 187, 189, 191, 197

68000....................................24, 26, 33, 41, 42
68020............................................................41


    8

8008..............................................................41
8080..............................................................41
8086........................................................26, 41
8088..............................................................41
80x86...............................................24, 26, 41


    A

ABLE............................................................67
accumulator...............21, 24, 31, 32, 33, 34, 57, 62, 82, 87, 88, 89, 90, 92, 93, 97, 99, 101, 103, 105, 106, 108, 111, 112, 114, 115, 118, 120, 132, 133, 134, 167, 168, 170, 171, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185,
186, 187, 188, 189, 205
activity packet..............................................139, 205
ADD..............................24, 49, 81, 83, 99, 155, 157
address bus..........................................................205
Altera...................................................................147
Amdahl, Gene......................................125, 126, 127
ANSI C...............................................................148
arithmetic logic unit (ALU)....................................205
assembler....................................................100, 205
assembly language...........xiii, xiv, 100, 101, 120, 122, 159, 160, 191, 205
associative memory......................................205, 206
atomic instruction.................................................205
Automatic Computing Engine (ACE)......................66
average................................................106, 108, 132


    B

B1700/B1800.......................................................66
Backus, John.................................................39, 123
Bell Laboratories...................................................42
biological computing..............................................18
Boehm, Corrado.....................................................15
Boehm-Jacopini Theorem................70, 71, 72, 78, 80
branch on zero (BNZ)...........................................63
bubble sort..................................................115, 116
Burroughs.............................................................66
 

 
 bus.....26, 31, 35, 66, 123, 138, 139, 145, 205, 206, 207, 209


    C

C language...............23, 26, 32, 100, 101, 102,   103
cellular automata........................................206
central processing unit..............29, 30, 31, 205,   206, 207, 208, 209, 210
Church, Alonzo......................................15, 69
Cocke, John................................................40
compiler..............42, 43, 44, 48, 66, 100, 122,    128, 132, 147, 148, 159, 160, 164, 197,    206
complete............17, 18, 29, 66, 75, 76, 77, 79, 80, 81, 83, 131, 153, 157, 160, 206
Completeness Theorem..........................69, 77
complex instruction set computer     (CISC)....................................17, 147, 206
complex instruction set computer
    (CISC)....17, 18, 47, 48, 49, 50, 51, 52, 53,     60, 131, 206
complexity      17, 47, 48, 49, 50, 51, 52, 56, 62, 63, 100, 127, 166
condition code register...............................206
conditional branch................23, 57, 62, 66, 79,      206
content-addressable memory......................206
Control Data Corporation............................42
control unit (CU)............................31, 39, 206
coprocessor..............................................206
Corporaal, Henk....................................15, 67
Cray I........................................................136
CRISP C-Machine......................................42
crossover...................................151, 152, 153
Crusoe.........................................................43
Culler...........................................................42
cycle stealing..............................................206
Cydrome.....................................................42


    D

data bus.....................................134, 137, 206
dataflow computer.............135, 139, 140, 205, 206
 DEC.................33, 40, 95, 103, 104, 110, 117, 168,       171, 180
decidability.............................................................69
decode..........................................47, 129, 130, 206
DesignWare.........................................................148
dilation...................153, 154, 155, 156, 157, 158, 159, 160, 191, 197, 201
Dinman, Saul....................................................15, 66
direct memory access (DMA)........30, 147, 206, 207
direct mode instruction.........................................207
DMA controller...........................................206, 207
DNA...........................144, 160, 161, 163, 164, 165
DRAM................................................................207
dynamic memory..................................................207


     E

effective instruction.....................60, 75, 92, 207, 208
erosion................................153, 154, 155, 156, 158
exception.................................................21, 26, 207
explicitly parallel instruction (EPIC)........................43, 52
explicitly parallel instruction computing
(EPIC)....................................................        43, 52


     F

fetch-execute cycle..............................207, 209, 210
field programmable gate array (FPGA)   
.......43, 44, 67, 145, 146, 147, 148, 149, 153, 157, 158, 160, 216
finite state automata (FSA).........................73, 74, 75, 160, 161, 162, 163, 207
fitness..........................................150, 151, 152, 153
flush.....................................................................207
Flynn, Michael.............................................135, 136
FORTRAN.....................................38, 39, 128, 164
fractal..................................................................144


    G

gene.............................................150, 151, 152, 153
general register...................................31, 50, 51, 207
Genetic Algorithm........................................149, 214
 greatest common denominator (GCD)
..........................................................119, 120
GRI 909......................................................66


    H

half adder (HA)...........55, 57, 58, 66, 83, 143, 146, 147, 153, 155, 158, 160, 164
Handel-C...................................................148
Harvard...........................................35, 37, 38
Hennessy.........15, 31, 34, 35, 41, 42, 56, 215
Hilbert, David..............................................69
Hoare, C.A.R............................................127
hypercube processor..........124, 135, 140, 208


    I

IBM......................33, 37, 38, 40, 41, 42, 214
IBM...............................................704 38, 39
IBM 801.....................................................40
IEEE 1364................................................148
immediate mode instruction........................208
implied mode instruction............................208
indirect mode instruction............................208
instruction parameterization..............59, 60, 92,    208
instruction register........................31, 207, 208
instruction sequencing.....................59, 92, 208
instruction synthesis..................48, 61, 92, 208
Intel....................................26, 33, 41, 43, 52
interrupt...............23, 24, 26, 30, 31, 180, 186,   187, 208, 210, 211
   controller..........................................31, 208
   handler location......................................208
   register...................................................208
   return location.........................................208
   vector  180, 186, 187, 208


    J

Jacopini, Giuseppe.................................15, 83
Java Virtual Machine..............................34, 66
     L

Laplante, Phillip..............................v, 39, 65, 66, 225
linear array processor...........................208, 209, 211
Lipovski, Jack..................................................15, 67
LISP..........................................................38, 39, 45


   M

machine code.........................32, 100, 102, 103, 104,     105, 128, 132, 205, 208
macrocode...................................................208, 209
macroinstruction.........................31, 39, 48, 137, 205,     206, 207, 208, 209
main memory.....................29, 30, 31, 47, 50, 66, 90,     91, 123, 205, 207, 209, 210
mask register........................................................209
Mavaddat, F..........................................................15
memory address register (MAR)....................31, 209
memory data register (MDR)..........................31, 209
mesh configuration................................................138
MicroBlaze..........................................................147
microcode....................................39, 42, 47, 48, 209
microcontroller.....................................................209
microinstructions...............................31, 48, 137, 209
micromemory...........................30, 31, 206, 207, 209
microprocessor..................xiv, 33, 41, 42, 43, 45, 52, 123, 128, 147, 167
microprogram................................................47, 209
Moore, S.W................................15, 67, 73, 74, 207
Morgan, G.......................................................15, 67
MOS Technologies................................................xiv
Motorola.............................................26, 33, 41, 42
MOVE
    instruction......................56, 59, 62, 63, 68, 81, 82,     83, 86, 88, 90, 93, 94, 96, 100, 105, 120, 132,     133, 134, 164
    OISC........................57, 85, 87, 88, 89, 100, 133,     152, 160, 167, 168, 176, 197
Multiflow...............................................................42
multiplexer...........................................................209
mutation...............................................151, 152, 153
MUX...............................................................     209
 
     N

New England Digital.....................................67
Nios..........................................................147
nonvolatile memory....................................209
non-von Neumann architecture.............18, 209
nop............................108, 118, 133, 134, 192


    O

object code........................................137, 209
occam-2....................................................140
OISC
   compiler..........................................147, 164
   continuum.................................................63
   one instruction set computer (OISC)
       instruction.....60, 61, 63, 87, 100, 131,           155, 165
opcode..........31, 77, 139, 205, 206, 208, 210
operand.............21, 22, 27, 57, 62, 85, 87, 89,     90, 91, 94, 95, 96, 97, 99, 100, 120, 139,     177, 178, 179, 180, 181, 182, 184, 185,     186, 187, 188, 205, 207, 208, 210
operandam........22, 23, 55, 56, 57, 58, 59, 61,     77, 82, 83, 86, 87, 88, 89, 90, 91, 93, 94,     97, 98, 99, 100, 120, 121, 152, 187, 188,     210
operandum........22, 23, 24, 26, 28, 55, 56, 57,     58, 59, 60, 61, 77, 82, 83, 86, 87, 88, 89,     90, 91, 93, 94, 95, 96, 97, 98, 99, 100,     105, 120, 121, 152, 187, 188, 210
operative...........................................165, 210


    P

parallel processing..........42, 52, 123, 124, 125,     126, 127, 128, 134, 135, 136, 137, 140,     141, 156, 157, 161, 206, 208
parallelism
   instruction......................................... 42, 141
   micro......................................128, 132, 136
Parvani, B.,..................................................15
Patterson, David....................................15, 42
Pentium.................................................24, 26

 
pipelining.............................................129, 132, 210
postfix notation..............................................24, 210
preempt...............................................................210
primary memory......................................90, 91, 210
processing element (PE).......................137, 138, 158,     210
program counter (PC)....................21, 23, 26, 31, 33,     41, 43, 56, 61, 63, 72, 73, 74, 76, 77, 78, 80, 81,     83, 99, 100, 101, 102, 103, 104, 106, 121, 157,     158, 179, 186, 189, 204, 206, 208, 210
propagation delay........................................138, 210
protein.........................................160, 161, 163, 164


   Q

Quicksort.....................................................127, 128


   R

reduced instruction set computer (RISC)
     17, 18, 34, 39, 40, 42, 47, 48, 49, 50, 51, 52, 53,      59, 60, 67, 90, 131, 135, 164, 210
register direct mode instruction.............................210
resultant..................22, 23, 24, 25, 28, 32, 34, 50,     57, 58, 59, 60, 77, 82, 83, 90, 91, 93, 94, 95, 97,     98, 99, 100, 121, 152, 158, 210
reverse subtract and skip on borrow (RSSB)      62
RISC I..................................................................42
RISC II.................................................................42
Rojas, Paul......................................................15, 79


   S

SBN
OISC..................................................85, 87, 88, 97
scratch pad memory.............................................210
selection......................70, 71, 72, 73, 74, 75, 76, 78,     79, 80, 151, 152, 156
self-modifying code..............................................211
Sierpinski Triangle................................................144
SOLOMON........................................................136

 
 
SPARC.................................................34, 42
speculative execution..................................211
speedup............................124, 125, 126, 127
SRAM.......................................................211
stack...........21, 24, 31, 32, 33, 34, 41, 52, 85,     86, 87, 92, 107, 108, 112, 115, 118, 120,     133, 134, 167, 168, 179, 180, 182, 184,     185, 186, 187, 211
stack architecture...........31, 32, 33, 34, 52, 85,     86, 87, 92
stack pointer.......................31, 180, 186, 211
Stanford University......................................42
static memory.............................................211
status register...........24, 25, 26, 31, 57, 62, 66,     72, 73, 74, 75, 76, 77, 78, 98, 121, 176,     178, 179, 184, 211
    subtract and branch if negative (SBN)
   55, 58, 61, 62, 63, 65, 66, 164
     instruction...........55, 57, 61, 68, 80, 81, 85,          88, 89, 91, 99, 100
Synopsys...................................................148
systolic processor......................135, 138, 211


    T

Tabak, Daniel........................................15, 67
Transmeta....................................................43
transputer...........................................140, 211
trap..............................................23, 100, 211
Turing computable......................79, 80, 81, 83
Turing, Alan.....................................15, 66, 69
    V

van der Poel......................15, 55, 56, 61, 65, 86, 87,     88, 89
van der Poel's Criterion..........................................61
VAX 11/780.........................................................40
vector processor..................................................211
Verilog................................................147, 148, 149
VHSIC Hardware Description Language     (VHDL).....................................65, 147, 148, 149
VLIW..............................................42, 43, 137, 214
von Neumann....................18, 38, 43, 123, 136, 140,     145, 211
    bottleneck................................................123, 211
    processor.................................................140, 211


   W

wavefront processor....................135, 137, 138, 211


   X

Xilinx............................................67, 147, 148, 216
XOR.................25, 66, 94, 95, 96, 98, 99, 121, 143,     162, 164, 180, 189, 211
    closure............................................................211


   Z

Zilog......................................................................41